Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/NXP Semiconductors/NeoM3/CANAF/FCANIE#0x0
FullCAN interrupt enable register
Global FullCAN Interrupt Enable. When 1, this interrupt is enabled.
Reserved. Read value is undefined, only zero should be written.
https://github.com/cmsis-svd/cmsis-svd-data